This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, in an attempt to inhibit degradation of read and write margins, some memory devices have attempted to support read and write operations by delaying data access signals in the signal timing path to recover read margins. In some cases, a dummy wordline (DWL) is used to track an actual wordline (WL), while a dummy bitline (DBL) is used to track an actual bitline (BL). Along with matching resistance (R), capacitance (C), and logic delays in a signal timing path, a local mismatch of bitcell transistors is evaluated and a reduction of bitcell current is compensated for. This may be taken care of by having additional delays in the data signal path, either by having less number of discharge cells or by increasing logic delays. However, this may result in a penalty in performance at a power, performance and area (PPA) corner, because degradation of bitcell current due to offset is less at the PPA corner, while the delays may be designed as per a read and write margin corner. Thus, there exists a need to improve integrated circuitry so as to enable recovery of degraded read and write margins in a more efficient manner.